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  1. Scholars Hub of the Academia Sinica
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Browsing by Author Hsiang-Yun Cheng


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Showing results 1 to 14 of 14
Issue DateTitleAuthor(s)RelationscopusWOSFulltext/Archive link
2015Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced InterferenceHsiang-Yun Cheng; Mary Jane Irwin; Yuan XieACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 21(1), 7:1-7:26
2010An Analytical Model to Exploit Memory Task SchedulingHsiang-Yun Cheng; Jian Li; Chia-Lin Yang
2015Cache and Memory Management Policies for Multi-Core SystemsHsiang-Yun ChengSIGDA Ph.D. Forum at DAC, 1-2
2015Core vs. Uncore: The Heart of DarknessHsiang-Yun Cheng; Jia Zhan; Jishen Zhao; Yuan Xie; Jack Sampson; Mary Jane Irwin
2016Designs of Emerging Memory Based Non-Volatile TCAM for Internet-of-Things (IoT) and Big-Data Processing: A 5T2R Universal CellMeng-Fan Chang; Ching-Hao Chuang; Yen-Ning Chiang; Shyh-Shyuan Sheu; Chia-Chen Kuo; Hsiang-Yun Cheng; John Sampson; Mary Jane Irwin
2018DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learningMeng-Yao Lin; Hsiang-Yun Cheng; Wei-Ting Lin; Tzu-Hsien Yang; I-Ching Tseng; Chia-Lin Yang; Han-Wen Hu; Hung-Sheng Chang; Hsiang-Pang Li; Meng-Fan Chang
2016Dswitch: Write-Aware Dynamic Inclusion Property Switching for Emerging Asymmetric Memory TechnologiesHsiang-Yun Cheng; Jishen Zhao; Jack Sampson; Mary Jane Irwin; Aamer Jaleel; Yu Lu; Yuan XieTechnical Report CSE-16-004, 1-10
2015EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip MultiprocessorsHsiang-Yun Cheng; Matt Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahumut Kandemir; Jack Sampson; Yuan XieACM Transactions on Architecture and Code Optimization 12(2),17:1-17:22
2014EECache: Exploiting Design Choices in Energy-Efficient Last-Level Caches for Chip MultiprocessorsHsiang-Yun Cheng; Matt Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahumut Kandemir; Jack Sampson; Yuan Xie
2015Energy-Efficient Inclusion Properties for STT-RAM Last-Level CachesHsiang-Yun Cheng; Matt Poremba; Ivan Stalev; Yuan Xie; Jack Sampson; Mary Jane IrwinNon-Volatile Memories Workshop (NVMW), 1-2
2016Exploiting and Accommodating Asymmetries in Memory to Enable Efficient Multi-core SystemsHsiang-Yun ChengPennsylvania State University Ph.D Thesis, 1-149
2016LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level CachesHsiang-Yun Cheng; Jishen Zhao; Jack Sampson; Mary Jane Irwin; Aamer Jaleel; Yu Lu; Yuan Xie
2018LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shufflingZhi-Lin Ke; Hsiang-Yun Cheng; Chia-Lin YangComputing Research Repository
2010Memory Latency Reduction via Thread ThrottlingHsiang-Yun Cheng; Chung-Hsiang Lin; Jian Li; Chia-Lin Yang
Showing results 1 to 14 of 14
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