| Issue Date | Title | Author(s) | Relation | scopus | WOS | Fulltext/Archive link |
|---|---|---|---|---|---|---|
| 2015 | Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference | Hsiang-Yun Cheng; Mary Jane Irwin; Yuan Xie | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 21(1), 7:1-7:26 | |||
| 2015 | Core vs. Uncore: The Heart of Darkness | Hsiang-Yun Cheng; Jia Zhan; Jishen Zhao; Yuan Xie; Jack Sampson; Mary Jane Irwin | ||||
| 2016 | Designs of Emerging Memory Based Non-Volatile TCAM for Internet-of-Things (IoT) and Big-Data Processing: A 5T2R Universal Cell | Meng-Fan Chang; Ching-Hao Chuang; Yen-Ning Chiang; Shyh-Shyuan Sheu; Chia-Chen Kuo; Hsiang-Yun Cheng; John Sampson; Mary Jane Irwin | ||||
| 2016 | Dswitch: Write-Aware Dynamic Inclusion Property Switching for Emerging Asymmetric Memory Technologies | Hsiang-Yun Cheng; Jishen Zhao; Jack Sampson; Mary Jane Irwin; Aamer Jaleel; Yu Lu; Yuan Xie | Technical Report CSE-16-004, 1-10 | |||
| 2015 | EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors | Hsiang-Yun Cheng; Matt Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahumut Kandemir; Jack Sampson; Yuan Xie | ACM Transactions on Architecture and Code Optimization 12(2),17:1-17:22 | |||
| 2014 | EECache: Exploiting Design Choices in Energy-Efficient Last-Level Caches for Chip Multiprocessors | Hsiang-Yun Cheng; Matt Poremba; Narges Shahidi; Ivan Stalev; Mary Jane Irwin; Mahumut Kandemir; Jack Sampson; Yuan Xie | ||||
| 2015 | Energy-Efficient Inclusion Properties for STT-RAM Last-Level Caches | Hsiang-Yun Cheng; Matt Poremba; Ivan Stalev; Yuan Xie; Jack Sampson; Mary Jane Irwin | Non-Volatile Memories Workshop (NVMW), 1-2 | |||
| 2016 | LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches | Hsiang-Yun Cheng; Jishen Zhao; Jack Sampson; Mary Jane Irwin; Aamer Jaleel; Yu Lu; Yuan Xie |
